Confidence Based Out-of-Order Renaming for Speculatively Multithreaded Processors

Speculatively multithreaded processors find parallelism by speculatively fetching and renaming dynamic flows of instructions from (perhaps) widely seperated parts of the program flow graph. These processors must handle inter-thread register dependences. The approach followed in this paper is to dynamically identify the consumers of interflow register mappings that will be (but have not yet been) produced in a logically earlier thread and then to dynamically awaken those consumers as soon as the mapping they are waiting for is produced. The main contribution of this paper is the design and evaluation of the inter-thread register renaming and synchronization mechanisms for a speculatively multithreaded processor that does not need compiler support. Our scheme is realizable, aggressive, and flexible and achieves speedups within about 10% of those achievable by an oracle. We find that inter-thread synchronization mechanisms can and must use path confidence information so that the producers of register mappings can awaken consumer instructions at just the right time, neither so early that the producer is on a misspredicted branch path, nor so late as to add latency to the critical path. We also demonstrate that a relatively straight-forward predictor can find the set of consumer instructions that must wait without being overly conservative.